Resume sample (Product Engineer)-EE

Name

address
Phone: 1-222-22222222

Email:xxxxxxxxxxxx


OBJECTIVE

A position to utilize my extensive experience and knowledge in standard cell library development.

QUALIFICATIONS

- Over three years experience with digital design tool
- Direct working experience in developing standard cell libraries.
- Hands-on experience with integrating commercial EDA tools into a local design flow
- Proficient in object oriented programming using Perl, C++/Java
- Solid working experience with shell scripts, C, VHDL/Verilog
- Experience with Linux/Unix environment
- Experience in direct support of design team
- Strong background in transistor-level circuit design in DSM
- Skillful in cell layout, analog circuit analysis
- Extensive working experience in digital circuit design from RTL to GDSII
- Expert in state-of-the-art synthesis, simulation, validation and library design EDA tools.
- Highly motivated team worker with effective self-learning and problem-solving abilities

TECHNICAL SKILLS

- EDA Tools: Synopsys Cadabra, DC, PT, Cadence Virtuoso, Layout Editor, PKS, NC-Verilog, Mentor Graphic Calibre, Xcalibre, ModelSim, ActiveHDL, HSPICE
- Programming Languages: Perl, Tcl/TK, shell scripts, VHDL/Verilog, C/C++, Java, UML, FORTRAN, Assembler (TI, Motorola)
- Software Development Kit: Eclipse, ARM ADS, MS Visual C++
- Software: MATLAB, Simulink, Rational Rose
- Design For Test: BIST development, ATPG algorithm, JTAG
- FPGA & Tools: Xilinx ISE, Foundation, System Generator, Virtex-E, Altera Quartus II, DSP Builder, Stratix-II
- Real-Time Operating System: TMS320xxx, ARM7TDMI, 68HC11
- Operation System: UNIX, Linux, Windows/NT

RELATED EXPERIENCE

Xx/2222 – present
xxxx Technologies Inc., US
CAD Engineer

Responsible for developing CMOS standard cells. In charge of developing, maintaining and support the automatic flow for library cell generation.

- Direct transistor-level circuit design, simulation and analysis.
- Cell layout using TSMC 0.13um, 0.09um technologies and post-layout validation, debugged failure cells, gave advice to the transistor circuit designers..
- Developed and released automatic cell library design flow, which integrated the state-of-the-art commercial tools for layout generation, DRC/LVS check, RC extraction and characterization. The new flow improved turn around time by 50% and was designed using perl, makefile, tcsh and Tcl.
- Support the design teams to ensure that the libraries function as required.
- Support the customers to ensure that the automatic library design flow incorporate with their working environment

Xx/2222-xx/2222
Xxxx Co. US
VLSI Design Engineer

In charge of developing virtual-library based logic synthesis tool for automatic full custom design in DSM. Focus on generating the transistor circuits that are optimized for specific design performance constraints. Involved in microprocessor and DSP design projects, responsible for RTL design, prototyping, modeling and logic/physical synthesis.
- Developed tree-based transistor topology extraction algorithm for cell layout estimation.
- Developed transistor-topology based cell delay estimation model for quick static timing analysis in 0.13um, 0.15um and 0.18um technologies.
- Developed technology-mapping algorithms for synthesizing logic circuit using custom cells. Improved area and power by 40% with these new algorithms at the same delay comparing to Synopsys DC; developed the software in C++.
- Designed DSP and microprocessor from RTL to GDSII; prototyped on Xlinx/Altera FPGA; modeled using SystemC 2.0 and VHDL.
- Designed 16-bit MIPS processor running at 400MHz using TSMC 0.18um technology. Focus on improving the through using scalar structure.
- Developed embedded pipelined CORDIC processor on ARM7TDMI Integrator/AP platform.
- Implemented embedded DDFS, FIR/IIR filters on TMS320C5401. The RTOS was written in assembler and debugged using Code Composer Studio.
- Designed the prototype system for base-band CDMA transceiver on Altera EP1S80 DSP Development Kit.

Xx/2222 - xx/2222
XXXX Corporation, Canada
ASIC Design Engineer

Involved in video image processing projects. Responsible for architecture design, RTL coding, functional verification at RTL/gate level, synthesis and design documentation.
- Developed BIST circuits for testing and diagnosing on-chip SDRAMs for stuck-at, bridging and address decoding faults.
- Designed FIFO controllers (about 50K gates each) and digital video signal format converters (about 200K gates each) using VHDL. Improved timing by 20% and area by 30% through carefully retiming.
- Designed testbenches using VHDL, TCL and Perl for chip level integration and verification; simulated and debugging the design.
- Chip-level synthesis at 0.18um technology. Setup design environment and constraints, inserting clock gating and scan chains. Optimized the architecture of the blocks.
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Xx/2222 – xx/2222
Xxxx co., China
Manager of Operations Department

Responsible for pre-sale and/or post-sale support of xxxx automatic control products/systems and project management. Duties include:
- Technical support in sales presentations, product demonstrations, proposal development and contract negotiations.
- Project schedule management, budget development and management.
- Negotiated with the owner for project schedule adjustment and engineering expense payment.
- Detailed hardware and software design and programming, commissioning and startup.
- Guiding the installation and maintenance of sensors/digital controllers to ensure that the system is functioning according to specifications.
- Training the operators and answering customer inquiries concerning system software and applications.
- Responsible for pre-sale support for the Building Automatic Control System of Shanghai Pacific Insurance Company Office Building. Supervised the design and implementation of the system. This system has about 1,500 control points, 25 DDCs and worth US$300,000.
- Took charge of the pre-sale technical support and implementation of Building Automatic Control System of Northeast Power Management Bureau Office Building project. This system has over 9,000 control points, 130 DDCs and worth US$700,000.
- In charge of the design and implementation the Building Automatic Control System of Wuxi Sheridan Hotel. This system has about 6,000 control points, 90 DDCs and worth US$600,000.
- Trouble-shoot the Automatic Control System of Wuhan Citroen Auto Manufactory with 5,000 control points, 100 DDCs and worth $1,000,000.

PUBLICATIONS

“xxxxxxxxxxx”, SPIE xxxxxxxxxxxxxxxxxxxxxxxxxxxxx

“xxxxxxxxxxxxx”, ICSE2004, Malaysia, time

"xxxxxxxxxxxxx", IEEE Northeast Workshop on Circuit and Systems, Montreal, time

EDUCATION

time

M. A. Sc. Xxxx University, Canada
Major in VLSI design methodology

time

M. A. Sc. xxxx University, Beijing, China
Major in Industrial Automatic Control System design

REFERENCES
Available as required

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